Memory Barrier

In the newer ARM processors (ARMv6 and above) it is architecturally defined that the software must perform a Data Memory Barrier operation every time a resource is either acquired or released, to ensure a consistent memory view to all running processes.

These newer processors can optimize the execution order of instructions and data accesses, but these optimizations may create speculative accesses to memory or out-of-order execution of instructions, leading to undesirable and unintended program behavior.

In those situations we want the processor to behave as the classical ARM processors and execute instructions and access memory in program order.

There are three types of barrier instructions, considering a uni-processor environment like the Raspberry Pi:

  • Data Synchronization Barrier (DSB) – does not complete until all the previous instructions complete;
  • Data Memory Barrier (DMB) – ensures that any explicit memory access after the DMB instruction only start when all explicit memory accesses before the DMB instruction complete;
  • Instruction Synchronization Barrier (ISB) – flushes the pipeline in the processor, so all the following instructions are fetched from cache or memory once the ISB completes.

The RPi BSP must then  implement a routine or macro that provides the DMB  inline assembly code, since several peripherals may need to access the same registers in the future (to use the MailBox interface, for instance).

The memory barrier instructions can be found at:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/I1014942.html

References:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dht0008a/CJAGIEIE.html
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka14041.html

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